Integrated circuits (ICs) are used in various applications and devices. Programmable circuits, e.g., field-programmable gate array (FPGA) devices, include logic blocks, generic structures and input/output structures that can be configured to perform any of a variety of functions and support different protocols. Devices may be coupled together or coupled to other components and communicate with one another through a master/slave configuration. As is generally known, a master/slave configuration is a system where one device is used to control one or more devices.
Generally, in order for the different components to communicate effectively, different reference clocks may be needed. For instance, a receiver that is coupled to receive a data stream with an embedded clock signal from a transceiver device may need a local reference clock. With two different clocks, possibly operating at different rates, the phase difference between the two clocks needs to be determined and the difference need to fall below the acceptable threshold, e.g., the frequency threshold, measured in parts per million (PPM), of the receiver.
For instance, the DisplayPort protocol may need two asynchronous clocks, i.e., one reference clock in the master device and another reference clock in the slave device. This creates a static clock rate difference between the two devices and may lead to higher jitter. Since there is a local reference clock source at the slave device, an additional phase-locked loop (PLL) circuit is required on the slave device. Dedicated clock pins may also be needed at the slave device to receive the clock signals from the local reference clock.
Other protocols, for instance the Peripheral Component Interconnect (PCI) Express protocol, may use a synchronized reference clock source. Therefore, there is no need for dedicated clock source on the slave device that is connected to a master device through such protocols. Compared to other protocols, e.g., Serial Advanced Technology Attachment (SATA), DisplayPort, etc., that use asynchronous clocks, protocols that use a synchronous clock has better jitter tolerance. However, the slave device requires dedicated clock pins to receive the synchronous clock input and a PLL circuit to adjust the phase of the synchronous clock at the slave device.